Panel Level Packaging Consortium Takes Up Its Work

Revolutionizing packaging technology: The Fraunhofer Institute for Reliability and Microintegration IZM is spearheading the transition from fan-out wafer to fan-out panel level packaging with an initiative that has brought together illustrious international partners – innovative SMEs as well as global players. The global nature of the partnership meant coping with often conflicting time zones. Michael Töpper, co-coordinator at the Fraunhofer IZM, recalls: “We called Asia in the morning, our European partners during the day, and spent the evenings on the line to America.”

A kick-off meeting was held on December 8th / 9th to coordinate the next steps on the journey. Full members with extensive voting rights at the meeting and supply chain members actively involved with production machines and material applications will include such high-profile names as Intel, ASM Pacific, Hitachi Chemical, AT&S, Evatec, NANIUM, Süss MicroTec, Unimicron, Brewer Science, FUJIFIM Electronic Materials U.S.A, ShinEtsu, Mitsui Chemicals Tohcello and Semsysco. With Fraunhofer IZM providing the development hub in Berlin, the members are dedicated to promoting the transition to the innovative production standard.

From Fan-out Wafer to Panel Level Packaging
Fan-out Wafer Level Packaging (FOWLP) is one of the latest packaging trends in microelectronics. FOWLP has a high potential for significant package miniaturization concerning package volume but also its thickness. Technological core of FOWLP is the formation of a reconfigured molded wafer combined with a thin film redistribution layer to yield an SMD-compatible package. Main advantages of FOWLP are the substrate-less package, low thermal resistance, improved RF performance due to shorter interconnects together with direct IC connection by thin film metallization instead of wire bonds or flip chip bumps and lower parasitic effects. Especially the inductance of FOWLP is much lower compared to FC-BGA packages. In addition, the redistribution layer can also provide embedded passives (R, L, C) as well as antenna structures using a multi-layer structure. It can be used for multi-chip packages for system-in-package (SiP) and heterogeneous integration. For higher productivity and resulting lower cost larger mold embedding form factors are forecast for the near future. Besides increasing wafer diameter an alternative option would be moving to panel sizes leading to fan-out panel level packaging (FOPLP). Here, panel sizes could range from 18”x24” (a PCB manufacturing standard) to even larger sizes.