Ultra-High-Density Interconnect: The Next Frontier for PCBs and IC Substrates

The electronics and microelectronics ecosystems are rapidly converging on a paradigm where the density and quality of interconnects drive system performance as decisively as transistor scaling. The Ultra-High-Density Interconnect (UHDI) electronics that AT&S is developing within the IPCEI ME/CT framework (Important Project of Common European Interest on Microelectronics and Communication Technology) capture this shift. In practical terms, UHDI refers to the ability to realize extremely fine line-and-spacing features in the single-digit micrometer range on build up layers, to deploy dense microvia architectures down to tens of micrometers in diameter, and to support tight bump and ball pitches suitable for multi die and chiplet systems.

UHDI is not only about cramming more metal into smaller spaces. It is about constructing a low-loss, low-skew, mechanically robust interconnect fabric that allows compute, memory, RF (Radio Frequency), and even photonics to coexist and communicate at unprecedented bandwidth densities, all within power, area, and cost envelopes acceptable to modern systems. UHDI improves insertion loss and reduces crosstalk, which in turn supports high speed channels. The technology also transforms power delivery: Denser, lower inductance power networks feeding increasingly dynamic AI (Artificial Intelligence) and HPC (High Performance Computing) engines respond faster to load transients and mitigate voltage droop. In short, UHDI converts the package from a bottleneck into a bandwidth and power integrity enabler.

“As a technology innovator, AT&S has been operating at the frontier of electronics miniaturization for a long time. We are ready to take the next step with our UHDI technology, which will open completely new avenues of exploration for our customers and partners. We are continually shrinking our systems and will be one of the first companies in the world to offer UHDI systems for advanced AI and datacenter applications. Our new IC Substrate Competence Center in Leoben and our participation in the IPCEI ME/CT will ensure our competitiveness for years to come,” says Markus Leitgeb, Head of Research BU ME at AT&S.

System‑Level strategy

With denser wiring, sub‑100‑micrometer bump pitches and fine redistribution layers, chiplet and multi‑die assemblies will move from concept to production. Designers can combine heterogeneous functions like compute tiles, HBM stacks (High-Bandwidth Memory), RF front‑ends, and optical components inside a single package and still meet aggressive performance and reliability targets. On substrates, fine‑line semi‑additive processes and high‑reliability microvia stacks open clean escape routes for massive pin counts without inflating layer counts or pushing packages to unwieldy footprints. On PCBs, UHDI makes module‑level compaction possible, enabling advanced system‑in‑package (SiP) concepts, embedded passives that shrink bill‑of‑materials and loop areas, and RF structures that are both compact and precisely controllable.

These advantages matter most in the applications defining the next decade. High‑performance computing and AI accelerators rely on vast I/O (Input/Output), clean power delivery, and extremely low‑loss links between logic and memory. Datacenter networking and 5G/6G infrastructure demand compact, low‑loss, high‑frequency interconnects and are already charting paths to co‑packaged optics to break the pluggable bandwidth wall. Automotive radar and advanced driver‑assistance systems need miniaturized RF front‑ends that remain stable and reliable across harsh thermal and vibration profiles. Consumer, medical, and industrial devices benefit from thinner modules, embedded functionality, and the ability to integrate sensing, computing, and connectivity in tiny footprints.

Challenges in UHDI scaling

The journey to UHDI is a full‑stack challenge where materials science, lithography, metallization, mechanical design, thermal engineering, inspection, and supply‑chain readiness must harmonize. As packages get larger and dielectric layers get thinner, the tolerance windows for flatness narrow. Warpage control becomes a central reliability and yield determinant not only at room temperature but through reflow and thermal cycling.

Reliability stresses that were marginal at coarser geometries become limiting as via diameters drop and stacks are built higher. Copper fatigue at interfaces, voiding in via fills, and conductive anodic filament (CAF) formation risk increase if chemistries, plating profiles, and dielectric choices are not precisely controlled. This is where AT&S’s Electronics Service Hub provides a decisive advantage for customers by utilizing advanced stress simulations and system design services that allow for system adjustments even before the first prototype is built.

On the factory floor, UHDI asks for high‑resolution lithography and laser drilling, plating chemistries that can reliably fill microvias without trapped voids, and inline metrology capable of resolving ultra‑fine features and buried structures.

AT&S UHDI roadmap

AT&S is pursuing UHDI along a clear, staged roadmap that ties advanced R&D to industrialization. In the near term, the focus is on hardening sub‑10‑micrometer line‑and‑space capabilities on build‑up layers, improving the reliability of stacked microvias through optimized fill chemistries and thermal‑mechanical design, and expanding the use of low‑loss dielectric platforms for high‑speed and mmWave structures. This phase also accelerates the integration of glass cores in pilot substrates (see previous blog post on Glass Core Substrates). Inline metrology and panel‑handling automation are being deployed to support repeatable yields as panel sizes grow.

In the midterm, AT&S is developing the needed building blocks on large panel formats, building a bridge from prototypes to high volume production. Collaboration with semiconductor partners intensifies around multi-die systems, high bandwidth memory interfaces, and the first co-packaged optics pilots, supported by substrate architectures that accommodate optical coupling while preserving electrical integrity and flatness. In the longer term, UHDI becomes a platform rather than a feature, with AT&S’s IC Substrate Competence Center in Leoben acting as the nucleus that connects exploratory research to manufacturable processes. This ensures that UHDI advances arrive with the reliability and scale demanded by top tier customers.

Looking ahead

As chiplets proliferate and optics edge closer to the package, the interconnect fabric’s density, loss, and mechanical stability will set the ceiling for performance. UHDI delivers the bandwidth density to move data where it needs to go, the power integrity to feed compute precisely when it is needed, and the manufacturability to do so at scale on large panels. The hard problems around warpage, reliability at small geometries, signal and power integrity at extreme frequencies and currents, inspection at micron scales, and supply‑chain readiness are being addressed through a combination of materials innovation, process control, metrology, and virtual design.

AT&S is committed to this path, translating R&D breakthroughs into production‑worthy platforms and partnering with customers to architect substrates and modules that realize the promise of UHDI. From AI accelerators and memory‑centric compute to high‑frequency communications and miniaturized modules, the roadmap is clear: UHDI will define the next decade of electronic systems, and AT&S is building the capabilities to make them real.