Multifunctional Cores: Turning the IC Substrate into a System Enabler

Microelectronics is accelerating toward a design paradigm where IC Substrates are no longer a passive intermediary but an active, co designed platform. As compute, memory, RF (Radio Frequency), photonics, and power delivery compress into ever tighter envelopes, the Multifunctional Core IC Substrate emerges as a decisive enabler. AT&S is developing this new technology within the framework of IPCEI ME/CT (Important Project of Common European Interest on Microelectronics/Communication Technology), and prototype manufacturing is already under way at the new Competence Center for R&D and IC Substrate Production in Leoben.

Within AT&S’s broader advanced packaging strategy, the Multifunctional Core transforms the substrate’s core from a simple mechanical and signal backbone into a high‑performance platform that integrates electrical, thermal, mechanical, and even optical functions. The result is not only denser routing and cleaner power; it is a substrate that allocates function to the physical center of the package, collapsing interconnect distances, reducing parasitics, and unlocking heterogeneous integration at meaningful scale.

A Multifunctional Core combines three pillars: First, the core becomes a power and thermal pathway, not just a structural element, distributing power in horizontal and vertical directions as well as channeling heat away from high power tiles and memory stacks while preserving planarity and reliability. Second, the core becomes a signal platform: low-loss dielectrics, controlled impedance structures, embedded passives, and precisely engineered reference planes stabilize high speed and high frequency. Third, the core becomes an integration anchor, accommodating through-core interconnects, glass or composite core materials, and coupling features that anticipate co-packaged optics and tight RF coexistence without sacrificing manufacturability. In practical systems, this means more layers devoted to function, enabling higher bandwidth density, lower loop inductance, and a packaging stack that contributes measurable performance per watt.

Challenges in scaling multifunctionality

Integrating multiple functions into the core concentrates benefits and complexity. Material compatibility is the first constraint: the coefficients of thermal expansion among glass, copper, and advanced dielectrics must be balanced to prevent interfacial stress accumulation through thermal cycles. Warpage windows narrow as packages grow and layers thin; Stresses that were marginal at coarser geometries become central as via diameters shrink and stacks grow taller.

As channels push toward extreme bandwidths and mmWave operation, the dielectric loss tangent and copper surface roughness inside and near the core become more important. Power distribution networks require low-inductance paths that do not compromise thermal structures or excite unwanted resonances.

AT&S addresses these constraints with a full-stack approach. The Electronics Service Hub couples multi-physics simulation, including thermal, electrical, and mechanical, to system-level design rules, enabling architectural adjustments before the first prototype is built. The outcome is not simply a set of isolated process wins, but a repeatable capability that can be transferred from pilot to volume.

AT&S’s multifunctional core substrate roadmap

In the near term, the focus is on hardening the building blocks: integrating thermally efficient planes and thick-copper-plated or even full-copper-filled through holes into cores that coexist with ultra-fine line/space buildup layers; improving the reliability of stacked microvias and through-core interconnects via optimized fill chemistries and thermomechanical stack design; and expanding low-loss dielectric platforms to ensure that high-speed channels retain fidelity as they traverse from die-side redistribution to core and back. This phase also advances Glass Core Substrates in pilot form, reserving optical coupling features and ensuring that mechanical flatness and bow remain within tight tolerances as panel sizes grow.

In the midterm, AT&S extends multifunctional cores across broader product families and larger panel formats, creating a robust bridge from prototypes to high‑volume production. Collaboration intensifies with semiconductor partners around multi‑die systems and high‑bandwidth memory interfaces, with the first co‑packaged optics pilots accommodated by core architectures that preserve electrical integrity while enabling optical alignment and coupling. Power delivery networks within the core evolve toward lower inductance and higher current capacity without incurring thermal penalties.

In the longer term, the Multifunctional Core becomes a platform rather than a set of features. Glass cores with through‑glass vias move from pilot to mainstream for large, high‑I/O packages that demand flatness, dimensional stability, and tight impedance control. Standardized core architectures enable chiplet ecosystems to mature around high‑density die‑to‑die interconnects, while heterogeneous integration expands to include RF, photonics, and sensing within package‑scale systems. Throughout this evolution, the AT&S Competence Center for R&D and IC Substrate Production in Leoben acts as the nucleus that connects exploratory materials and processes to manufacturable, reliable products for top‑tier customers.

Chiplets and optics

As chiplets proliferate, bandwidth walls shift from on‑die fabrics to the interfaces that bind systems together. As optics move closer to compute and RF modules crowd into tighter spaces, the stability, density, and multi‑physics performance of the substrate set the ceiling for the entire system. The Multifunctional Core IC Substrate meets this moment. It supplies the thermal headroom to keep accelerators and memory on their efficiency curves. It delivers the low‑loss, low‑skew interconnect fabric needed for ultra‑high‑speed channels. It brings power integrity from a reactive exercise in mitigation to a proactive element of the architecture. And it does so in a form factor and cost envelope aligned with volume manufacturing on large panels.